1. Field of the invention
The present invention relates to the field of differential-to-single-ended translator circuits. More particularly, the present invention relates to such translator circuits that are CMOS-based. More particularly yet, the present invention relates to such CMOS translators where speed is of the essence, yet the translator design must be usable over a wide range of output loads. Most particularly, the present invention relates to such CMOS translator circuits needed to function under conditions requiring such translators to operate at very high speed while driving large output loads.
2. Prior Art
Differential-to-single-ended translators are used in a variety of applications to convert a differential input signal into a single-ended output signal. The differential input signal will be provided by two lines that in general have no well-defined reference level, and may in general be floating, where the input signal equals the difference in potential between the two lines. The single-ended output is referenced to a fixed potential, typically ground. In general, the signal is a digital one, consisting of a series of logic-high and logic-low values. Apart from providing differential-to-single conversion, these translators are also used to increase the amplitude of the incoming signal pair, to the extent necessary, in order to provide a signal that is robust enough to be useful in subsequent stages. For purposes of describing the background and novelty of the present invention, the term "translator," unless qualified further, will be used to refer to a differential-input-to-single-ended-output translator. Furthermore, the term will be limited to such translators that are MOSFET-based rather than bipolar-transistor-based. At places, the translator will be discussed as a combination of an input amplifier stage and a converter stage, the input amplifier stage producing an intermediate differential signal that is amplified with respect to the input differential signal, and the converter stage doing the actual conversion of the (amplified) differential signal to a single-ended signal.
Kuo (U.S. Pat. No. 5,491,455 issued Feb. 13, 1996, and assigned to National Semiconductor Corporation) sets out a CMOS translator. FIG. 1 (Prior Art) illustrates the heart of the Kuo translator circuit, with the input amplifier stage not shown. Unfortunately for general applications, the circuit taught by Kuo does not function properly under certain output load situations. Furthermore, there is an asymmetry in the operation of the Kuo translator that limits its use in other ways. However, the most serious problem is that of dealing with large loads. With reference to FIG. 1, it can be seen that the single-ended output of the translator goes into an inverter. The larger the inverter the greater the capacitive loading on Vout and the longer it takes to drive Vout (and the inverter input) HIGH. (It is with the transition LOW to HIGH that the problem arises, rather than existing for both transitions, one of the consequences of the asymmetry of the Kuo translator.) Now, it is inherent in the Kuo circuit that the current driving Vout HIGH is provided for a limited time interval following a logic switch in the input signal, and that after that the current is cut off. It can happen, therefore, that before sufficient drive current has been supplied to make Vout HIGH, this cutoff occurs, leaving Vout floating somewhere between LOW and HIGH. This has obvious detrimental consequences for the operation of any circuit depending on the translator.
One fix to the problem is to use a series of CMOS invertors. This allows a large total gain without requiring that Vout look into a single large capacitance. A series of small-area invertors can give the same overall gain as a single large-area inverter, while appearing to Vout to have just the capacitance of the initial one. This solution is workable as long as the circuit in which the translator is being used can tolerate the reduced switching speed that interposing a series of invertors in the signal path leads to. Of course, even under those tolerant circumstances, the use of a number of real-estate-consuming invertors is generally not desirable.
To see in particular the problem with the Kuo translator, refer again to FIG. 1. This is the converter stage of that translator. Consider IN switched LOW (and IN_BAR HIGH). The input IN then turns off N5 and N4. IN_BAR HIGH turns N2 and N3 on. The drain of N3 is LOW because of the coupling through initially-on N6 to the low-voltage power rail. This causes a LOW voltage to be applied to the gate of P3, which turns on, coupling Vout to Vcc. However, N2 remaining on hard (because of IN_BAR HIGH maintaining the gate voltage of N2 HIGH) means that a link is established between the drain of N2 and GROUND through always-on N7. In a very short time, this will pull the drain of drain-gate-coupled N1 LOW. Since this point is connected directly to the gate of N6, this will shut N6 off after a certain interval. This in turn cuts Vout off from its link to Vcc and allows it to float. In those circumstances where Vout had not yet passed the threshold into HIGH, it never will. Those circumstances are the ones where Vout is looking into a large load. As set out above, the "fix" that is available for this, using a series of small invertors in place of one large one, degrades the through-put signal speed, something that cannot be tolerated in a number of important applications.
What is needed, therefore, is a differential-to-single-ended translator circuit that can service a wide range of loads with no basic design change. What is also needed is such a circuit that does not result in increased chip-area demands, a circuit that is simple and demands minimal power. Finally, what is needed is such a circuit that makes no compromises in speed in order to accommodate a wide range of loads.